
    L&iW                         d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZmZ g dZ G d de          Z G d d	e          Z G d
 de          ZdS )z
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2022 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
    N)
RegexLexerbygroupsincludeusingthiswords)	TextCommentOperatorKeywordNameStringNumberPunctuation
Whitespace)VerilogLexerSystemVerilogLexer	VhdlLexerc                      e Zd ZdZdZddgZdgZdgZdZde	j
        dfd	efd
 eej        e          fde	j        fde	j        fdefdedfdej        fdej        fdej        fdej        fdej        fdej        fdej        fdefdej        fdefdefdej        fd eeej        e          fd eeej        e          df edd !          ef ed"d#d $          e	j
        f ed%d&d $          ej         f ed'd !          ej!        fd(ej"        fd)efd*efgd+ed,fd-ej        fd.efd
 eej        e          fd/efgd0e	j
        fd1e	j        fd2e	j        d,fd3e	j
        fd4e	j
        fd5ed,fgd6ej        d,fgd7Z#d8 Z$d9S ):r   zZ
    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    verilogvz*.vztext/x-verilog(?:\s|//.*?\n|/[*].*?[*]/)+z^\s*`definemacro\s+(\\)(\n)/(\\\n)?/(\n|(.|\n)*?[^\\]\n)/(\\\n)?[*](.|\n)*?[*](\\\n)?/[{}#@]L?"string4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?(\d+\.\d*|\.\d+|\d+[fF])[fF]?z([0-9]+)|(\'h)[0-9a-fA-F]+z([0-9]+)|(\'b)[01]+z([0-9]+)|(\'d)[0-9]+z([0-9]+)|(\'o)[0-7]+z\'[01xz]z\d+[Ll]?[~!%^&*+=|?:<>/-][()\[\],.;\']`[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import)qalwaysalways_comb	always_ffalways_latchandassign	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamstrengthr    strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor\bsuffix)
accelerateautoexpand_vectornets
celldefinedefault_nettyperB   elsifendcelldefineendif
endprotectendprotectedexpand_vectornetsifdefifndefr   noacceleratenoexpand_vectornetsnoremove_gatenamesnoremove_netnamesnounconnected_driveprotect	protectedremove_gatenamesremove_netnamesresetall	timescaleunconnected_driveundef`)prefixr   )4bits
bitstorealbitstoshortrealcountdriversdisplayfclosefdisplayfinishfloorfmonitorfopenfstrobefwrite
getpatternhistoryincsaver\   itorkeylistlogmonitor
monitoroff	monitoronnokeynologprinttimescalerandomreadmembreadmemhrealtime
realtobitsresetreset_countreset_valuerestartrtoisavescalescopeshortrealtobits
showscopesshowvariablesshowvars	sreadmemb	sreadmemhstimestopstrobetime
timeformatwritez\$)byteshortintintlongintr]   r   bitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewandworshortrealrealr   [a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*\\(\S+)"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})	[^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]/z//.*?\n/	(?<=\\)\n\n	[\w:]+\*?rootr    r   r)   c                 @    d}d| v r|dz  }d| v r|dz  }d| v r|dz  }|S )z`Verilog code will use one of reg/wire/assign for sure, and that
        is not common elsewhere.r   r   g?r   r/    )textresults     `/home/geonatureadmin/si_en_reseau/tutos/venv/lib/python3.11/site-packages/pygments/lexers/hdl.pyanalyse_textzVerilogLexer.analyse_text   sF     D==cMFT>>cMFtcMF    N)%__name__
__module____qualname____doc__namealiases	filenames	mimetypes_wsr
   Preprocr   r   r   EscapeSingle	Multiliner   Charr   FloatHexBinIntegerOctr   r   Constantr   	Namespacer	   r   BuiltinTypeLabeltokensr  r  r  r  r   r      s        
 D#GI!"I )C W_g6Z ((6=*==>-w~>.0AB$VX&DfkR5v|D-v|<*FJ7#VZ0$fn5$fj1&!&.)!8,{+t}-$hhz7;Ld&S&ST#XXj':KT%R%R U :" CH#I I I$ %( U  "&e5 5 5 _ U W U	, 	, 	, \
 U 1 :?	@ @ @
 \ #DJ/&WL
\ 66"?O6"((6=*==>FO
 ) '"3407?#7?+J'
 4>62
{` `FD    r  r   c            
          e Zd ZdZdZddgZddgZdgZdZg d e	e
ej                  d	fd
 e	e
ej        e
          fd e	e
ej        e
          dfde
fd e	ej        e
          fdej        fdej        fdefdedfdej        fdej        fdej        fdej        fdej        fdej        fdej        fdefdej        fdef edd           ej        fd!efd"ej        f ed#d           efd$ e	ej         e
ej!                  fd% e	ej         e
ej!                  fd& e	ej         e
ee
ej!                  f ed'd           ej"        f ed(d           ej        f ed)d           ej#        fd*ej$        fd+efd,efd-ed.fd/ej        fd0efd e	ej        e
          fd1efgd2ej        fd3ej        fd4ej        d.fd5ej        fd6ej        fd7e
d.fgd8ej        d.fgd9Z%d:S );r   z
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    systemverilogsvz*.svz*.svhztext/x-systemverilogr   z^(\s*)(`define)r   r'   r(   r)   r   r   r   r   r   r   r    r!   r"   r#   z4([1-9][_0-9]*)?\s*\'[sS]?[bB]\s*[xXzZ?01][_xXzZ?01]*z6([1-9][_0-9]*)?\s*\'[sS]?[oO]\s*[xXzZ?0-7][_xXzZ?0-7]*z6([1-9][_0-9]*)?\s*\'[sS]?[dD]\s*[xXzZ?0-9][_xXzZ?0-9]*zB([1-9][_0-9]*)?\s*\'[sS]?[hH]\s*[xXzZ?0-9a-fA-F][_xXzZ?0-9a-fA-F]*z
\'[01xXzZ]z[0-9][_0-9]*r$   )insidedistr   r   z[()\[\],.;\'$]r&   )	accept_onaliasr*   r+   r,   r-   r.   assertr/   assumer0   beforer1   bindbinsbinsofr2   r3   r4   r5   r6   r7   r8   cellcheckerclockingr9   config
constraintcontextr;   cover
covergroup
coverpointcrossr<   r=   r>   designr?   r@   rA   rB   rC   rD   
endcheckerendclocking	endconfigrE   rF   endgroupendinterfacerG   rH   rI   
endprogramendpropertyendsequencerJ   rK   rL   rM   
eventuallyexpectexportexternrO   first_matchrP   rQ   foreachrR   rS   forkjoinrT   rU   rV   globalrW   rX   rY   iffifnoneignore_binsillegal_binsimplies
implementsr)   incdirr   rZ   r[   r\   instanceinterconnect	interface	intersectr^   join_any	join_noner_   letliblistlibrarylocalr`   ra   matchesrb   modportrc   rd   re   nettypenewnexttimerf   rg   noshowcancelledrh   ri   rj   nullrk   rl   packagerm   rn   ro   rp   rq   priorityprogrampropertyr   rr   rs   rt   ru   pulsestyle_ondetectpulsestyle_oneventpurerandrandcrandcaserandsequencerv   rw   	reject_onrx   ry   restrictrz   r{   r|   r}   r~   r   s_alwayss_eventually
s_nexttimes_untils_until_withr   sequenceshowcancelledr   softsolver   r   staticstrongr   r   r   supersync_accept_onsync_reject_onr   taggedr   r   
throughouttimeprecisiontimeunitr   r   r   r   unionuniqueunique0until
until_withuntypeduser   virtualr   
wait_orderweakr   r   r   wildcardwithwithinr   r   z(class)(\s+)([a-zA-Z_]\w*)z(extends)(\s+)([a-zA-Z_]\w*)z,(endclass\b)(?:(\s*)(:)(\s*)([a-zA-Z_]\w*))?)!r   r   chandler:   rN   r   r]   r   r   r   r   r   r   	shortrealr   r    r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   r   wor)z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)z$exitz$finishz$stopz	$realtimez$stimez$timez$printtimescalez$timeformatz$bitstorealz$bitstoshortrealz$castz$itorz$realtobitsz$rtoiz$shortrealtobitsz$signedz	$unsignedz$bitsz$isunboundedz	$typenamez$dimensionsz$highz
$incrementz$leftz$lowz$rightz$sizez$unpacked_dimensionsz$acosz$acoshz$asinz$asinhz$atanz$atan2z$atanhz$ceilz$clog2z$cosz$coshz$expz$floorz$hypotz$lnz$log10z$powz$sinz$sinhz$sqrtz$tanz$tanhz
$countbitsz
$countonesz
$isunknownz$onehotz$onehot0z$infoz$errorz$fatalz$warningz$assertcontrolz$assertfailoffz$assertfailonz$assertkillz$assertnonvacuousonz
$assertoffz	$assertonz$assertpassoffz$assertpassonz$assertvacuousoffz$changedz$changed_gclkz$changing_gclkz$falling_gclkz$fellz
$fell_gclkz$future_gclkz$pastz
$past_gclkz$rising_gclkz$rosez
$rose_gclkz$sampledz$stablez$stable_gclkz$steady_gclkz$coverage_controlz$coverage_getz$coverage_get_maxz$coverage_mergez$coverage_savez$get_coveragez$load_coverage_dbz$set_coverage_db_namez$dist_chi_squarez$dist_erlangz$dist_exponentialz$dist_normalz$dist_poissonz$dist_tz$dist_uniformz$randomz$q_addz$q_examz$q_fullz$q_initializez	$q_removez$async$and$arrayz$async$and$planez$async$nand$arrayz$async$nand$planez$async$nor$arrayz$async$nor$planez$async$or$arrayz$async$or$planez$sync$and$arrayz$sync$and$planez$sync$nand$arrayz$sync$nand$planez$sync$nor$arrayz$sync$nor$planez$sync$or$arrayz$sync$or$planez$systemz$displayz	$displaybz	$displayhz	$displayoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz$strobez$strobebz$strobehz$strobeoz$writez$writebz$writehz$writeoz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$rewindz$sformatz	$sformatfz$sscanfz$swritez$swritebz$swritehz$swriteoz$ungetcz	$readmembz	$readmemhz
$writemembz
$writememhz$test$plusargsz$value$plusargsz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsr   r   r  r  r  r  r  r  r  r  z//.*?$r	  r
  r  r  r  N)&r  r  r  r  r  r  r  r  r  r   r   r
   r  r   r*  r   r   r!  r"  r   r#  r   r$  r&  r(  r'  r%  r   r   Wordr   r)  DeclarationClassr,  r+  r-  r.  r  r  r  r   r      sd         D%G!I'(I )C}
*go!F!FP}
$hhz7;Lj&Y&YZ}
 $XXj':KZ%X%XZbc}

 Z }
 ((6=*==>}
 .w~>}
 /0AB}
 $}
 VX&}
 EfkR}
 6v|D}
 .v|<}
  EZ!}
$ GZ%}
( G^)}
, SZ-}
2 F#3}
4 fn-5}
8 "8,9}
: U%e444hmD;}
> ,?}
@ t}-A}
D U (R S) ) )T U*E}
\ +Xg):tzBBD]}
` -Xg):tzBBDa}
d =Xg):{JPTPZ[[]e}
j U @ 	 	 	 \
k}
B U N    _C}
T U MZ  [M! M! M!\ \]NU}
t #DJ/u}
v  &w}
x y}
~ 66"?O6"((6=*==>FO
 ) '"34/7?#7?+J'
 4>62
]Q QFFFr  r   c                   v   e Zd ZdZdZdgZddgZdgZej	        ej
        z  Zdefd eej        e          fdej        fd	ej        fd
efdej        fdefdefd eeeej                  fd eeee          fd eeeej        e          fd eeeej                  fd eej        ej                  f edd          ej        fd eeeej                  fd eeeej        eeeej        ee	  	        fd eej        eee          fd e ee          e          df ed           ed           ed          defg ed          dej        fdefded fg ed!d          ej        fg ed"d          efgd#ej         fd$ej         fd%ej!        fd&ej"        fd'ej#        fd(ej$        fgd)Z%d*S )+r   z:
    For VHDL source code.

    .. versionadded:: 1.5
    vhdlz*.vhdlz*.vhdztext/x-vhdlr   r   z--.*?$z'(U|X|0|1|Z|W|L|H|-)'r$   z
'[a-z_]\w*r%   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))stdieeeworkr   r   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*;r  )booleanr   	characterseverity_levelr]   r   delay_lengthnaturalpositiver    
bit_vectorfile_open_kindfile_open_status
std_ulogicstd_ulogic_vector	std_logicstd_logic_vectorr   r   )_absaccessafterr5  allr.   architecturearrayr6  	attributer1   blockbodybufferbusr6   	componentconfigurationconstant
disconnectdowntorB   r   rC   entityexitfilerP   rT   rU   genericgroupguardedrY   impureininertialr[   islabelrf  linkageliteralloopmapmodrd   rk  nextrg   rh   rn  ofonopenrk   othersoutro  port	postponed	procedureprocessru  rangerecordregisterrejectremrz   rolrorselectseveritysignalsharedslasllsrasrlsubtypethento	transportr   unitsr  r  variabler   whenr   r  r   r   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r  r  r  r  r  N)&r  r  r  r  r  r  r  r  re	MULTILINE
IGNORECASEflagsr   r   r   r   r
   r!  r#  r   r   	Attributer   r   r*  r   r  r   r   r   r,  r   r'  r$  r%  r(  r&  r.  r  r  r  r   r   u  s        
 DhG7#IIL2=(E Z ((6=*==>'%v{3!8,DN+{+V$)Xgz4>::<"HHWj'$J$JK/Xgz4>7CCE(Xgz4>::<'Xdndn557U*5999^2Xgz4:668.Xgz4:z7Jj*g7 78 1Xdj(J@@BHHUU4[[*==zJGGGJGI4 G$
L GJ4:&Z ;'	
 U G PU	V V V
 \
 U 0  9>!? ? ?" #
* %fn5V^$-v|<vz*FJ'6:&
QP PFFFr  r   )r  r  pygments.lexerr   r   r   r   r   r   pygments.tokenr	   r
   r   r   r   r   r   r   r   __all__r   r   r   r  r  r  <module>r      si    
			 L L L L L L L L L L L L L L L L$ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ $ >
=
={ { { { {: { { {|` ` ` ` ` ` ` `F\ \ \ \ \
 \ \ \ \ \r  